Existing methods and electronic devices employ up to 3 additional mask levels in order to integrate high precision thin film resistors (TFRs) having sufficient accuracy and matching characteristics.
FIG. 11 is a simplified schematic of an integrated circuit with a thin film resistor which is manufactured according to the prior art. The thin resistive layer of the TFR is embedded in an insulating IMDn−1 layer and is connected to a conductive METn layer with shallow VIAs referred to as TFVIA. The shallow connection adds only a low parasitic value to the resistance of the TFR. A deeper VIAn connects the METn layer to the METn−1 layer of the circuit interconnection. Due to the sensitivity of the thin resistive layer to overetching, two separate photo- and etching sequences are used for the shallow TFVIA and the deeper VIAn. This method requires at least 2 additional mask levels in the BEOL process to integrate the TFR.
However, any additional mask level renders the process flow more complex and expensive. Solutions using fewer mask levels either result in lower resistor performance or in an interact with the baseline interconnect processes. Thin film resistors are usually made of NiCr or SiCr alloys and they are typically located between two consecutive metallization levels. In order to prevent erosion of the thin resistor film during typical etching processes while at the same time providing a shallow connection with low parasitic resistance, either a separate thin film resistor head or a separate thin film VIA or both are usually provided.